Date of Completion

1-20-2017

Embargo Period

1-20-2017

Keywords

SWSFETs; multi-channel FETs; ADC; VLSI; SRAM; QWell FET, SiGe

Major Advisor

Faquir Jain

Co-Major Advisor

John Chandy

Associate Advisor

John Ayers

Associate Advisor

Lei Wang

Associate Advisor

Evan Heller

Field of Study

Electrical Engineering

Open Access

Open Access

Abstract

This dissertation aims at developing circuit models for complementary (n- and p-channel) spatial wavefunction switched field-effect transistors (SWS-FETs). Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The development of SWS-FET logic gates and quaternary logics using sub 25 nm FETs is presented. In addition, simulation of compact 3-bit Analog-to-Digital Converters (ADCs) is presented. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The models are based on the integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The simulation results show using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

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