Date of Completion

7-16-2014

Embargo Period

7-11-2024

Major Advisor

Mohammad Tehranipoor

Associate Advisor

John Chandy

Associate Advisor

Lei Wang

Associate Advisor

Omer Khan

Associate Advisor

A. F. M. Anwar

Field of Study

Electrical Engineering

Degree

Doctor of Philosophy

Open Access

Campus Access

Abstract

As manufacturing technology scales down to 65nm and below, fabricated chips are becoming increasingly vulnerable to timing-related defects and parametric failures. This leads to increased yield loss and escape and reduced reliability. Scan-based at-speed delay test is becoming an indispensable method for nanometer technology designs to target the timing-related failures. However, the delay test patterns that are generally generated cannot meet the specific requirements raised from manufacturing test experience. In this work, we develop techniques to target several practical test pattern issues. The first is Small-delay defect (SDD) pattern generation using timing-aware method or N-detect method is extremely time-consuming and requires very large memory to store the test data. This is not affordable for most IC companies thus both of them are rarely used in practice. The second issue is the widely used transition delay test patterns which are generated using 1-detect method have very low SDD coverage which is not acceptable to guarantee low DPM level. A pattern set that has a compact size as well as satisfying SDD coverage is highly required. The third issue is comparing with functional test pattern, delay test pattern (structural test pattern) cannot provide a reliable result in the speed binning process because of inaccurate mimicking functional running status. It is highly possible that the incorrectly binned chips would fail in the field, thus increase customer return and reduced profitability. The performance mismatch between delay test and functional test needs to be reduced. Besides, In order to solve above problems, we propose novel testing techniques including: (1) TDF pattern selection and pattern evaluation using critical faults; (2) Compact TDF pattern generation to maximize SDD coverage; (3) Worst-case path-based delay test generation considering power supply noise (PSN). The developed procedures help improve yield, reliability and reduce the test cost. Based on the research investigation and development, test time reduction, speed binning delay test generation, and physical diagnosis are also implemented in the industrial work derived from the research topics within this program.

Available for download on Thursday, July 11, 2024

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