Title

Layout-Aware Delay Fault Testing Techniques Considering Signal and Power Integrity Issues

Date of Completion

January 2010

Keywords

Engineering, Computer|Engineering, Electronics and Electrical

Degree

Ph.D.

Abstract

In current technologies (65nm and beyond), functional failures caused by shorts, opens, and stuck-at faults do not seem to be the main issues; instead, timing related parametric failures are on the rise and are expected to increase as technology further scales [1]. This leads to increased yield loss and escape and reduced reliability. As a result, at-speed test is a requirement for nanometer technology designs to target timing-related failures. Structural at-speed tests, scan-based transition delay fault (TDF) and path delay fault (PDF) tests, are widely adopted because of their low implementation cost and high test coverage [2]. However, as circuit complexity and functional frequency increase, the test power consumption, supply voltage noise, crosstalk, and hot spots caused by nonuniform on-chip temperature will significantly impact yield and reliability. Timing failures are often the result of a combination of weak points in a design and silicon abnormalities [3], which reduce the noise immunity of the design and expose it to signal integrity (SI) issues. For example, a poor power planning or missing power vias can incur on-chip power droop for some test vectors. The power droop can impact a gate(s) on a critical path and it may cause timing failure. This failure may only be excited with certain test vectors as inputs. If the corresponding test vector is not included in the test pattern set, the failure becomes an escape and cannot be reproduced during diagnosis with the current test pattern set. In this work, we target these challenges and propose novel layout-aware testing techniques to deal with the power and timing integrity issues. These techniques include: (1) Test pattern generation to detect weak area (open/resistive open, missing vices) in the layout design; (2) Test pattern generation to maximize the power supply noise around critical paths for verification purpose; (3) Diagnostic pattern generation to distinguish parametric failures from failures caused by physical defects; and (4) Pattern evaluation in terms of path delay increase caused by noises. These procedures help improve yield, reliability and reduce the time to market.^