Title

Design of Reliable and Energy-Efficient Nanoscale Integrated Systems

Date of Completion

January 2011

Keywords

Engineering, Computer|Engineering, Electronics and Electrical|Nanotechnology

Degree

Ph.D.

Abstract

Emerging nano-scaled electronics such as silicon nanowires (NW) and quantum-dot cellular automata (QCA) demonstrate great potential for continuing the technology advances toward future nanocomputing paradigm. However, excessive defects from bottom-up stochastic assembly have emerged as a fundamental obstacle for achieving reliable computation using these nano-scaled electronics. In this dissertation we present an information-theoretic approach to investigate the intrinsic relationship between defect tolerance and inherence redundancy in systems built upon nanowires and QCAs. By modeling these defect-prone electronics as a non-ideal information processing medium, we determine the information transfer capacity, which can be interpreted as the bound on reliability that a molecular crossbar system can achieve. The proposed method allows us to evaluate the effectiveness of redundancy-based defect tolerance a quantitative manner. Employing this method, we derive the gap of reliability between redundancy-based defect tolerance and ideal defect-free molecular systems.^ Besides the reliability issue, high energy dissipation of modern VLSI systems has been another concern of great importance due to the large scale, ultra high clock frequency, and very complex mechanisms implemented in those systems. Since nano-scaled electronics such as nanowire have shown their great potential for building memories and memory-like structures consume large amount of energy, this dissertation also discusses techniques to reduce the energy consumption of a memory-like structure, on-chip caches, which contribute large part of energy dissipation consumed by microprocessors. Specifically, this dissertation explores two directions in developing new cache architectures to improve the energy efficiency of data caches in microprocessors at the cost of negligible performance degradation. One is referred to as way-tagged (WT) cache while the other is named as early tag access (ETA) cache. WT cache records the way information of data, which indicates which way the data resides in the L2 cache. In write-through cache systems, if there is a write hit in the L1 data cache, the subsequent cache access on the L2 cache only needs to activate its destination way with the help of the recorded way information for the data. ETA cache performs early accesses to an additional tag array to determine the destination way information prior to actual cache accesses. It thus allows only the destination way to be accessed if a hit occurs during the early tag access. Due to these new features, the potential cache architectures are very effective in reducing the number of ways accessed during cache accesses. This enables significant energy reduction with negligible or even no performance overhead. ^