Title

Multi-objective Application-specific Instruction set Processor Design: Towards High Performance, Energy-efficient, and Secure Embedded Systems

Date of Completion

January 2011

Keywords

Engineering, Computer|Engineering, Electronics and Electrical

Degree

Ph.D.

Abstract

Application-Specific Instruction set Processor (ASIP) has become an increasingly popular platform for embedded systems because of its high performance, great flexibility, and short turn-around time. Multiple requirements on such processors have been imposed by the rapidly developing embedded application market. Such requirements include high performance, high energy efficiency, small circuit size and high security and reliability. ^ In this dissertation, we develop a holistic multi-objective ASIP design flow to target these design goals. The design flow includes three major steps - custom instruction set selection, custom hardware extension generation, and the underlying microarchitecture optimization. We propose to formulate the custom instruction selection problem based on "Operation Scheduling". Both Mixed Integer Linear Programming (MILP) and Simulated Annealing (SA) algorithms are developed to efficiently identify a set of custom instruction candidates, targeting performance, energy efficiency, or area overhead reduction. This technique identifies custom instruction set that can achieve 1.64 performance speedup and 29.8% energy reduction on average for a set of Mibench applications with a tolerable hardware overhead. Configurable Custom Function Units (CCFUs) to execute the custom instructions are automatically generated along the ISA synthesis process. We develop a resource sharing technique that yields 41.2% hardware overhead reduction for these CCFUs. To further optimize the microarchitecture of ASIP, we extend the custom register usage by allowing the basic instructions to access them during their idle time through a hardware/software co-design process. We achieve 11.7% reduction of execution cycles on average by substituting 19.3% of the off-chip memory accesses with much more light-weight on-chip data communications between the general purpose register file and the custom registers. At the micro-architecture level, we further extend the processor datapath to incorporate a new Code Integrity Checker (CIC) for monitoring instruction integrity at run-time. Both security and reliability are enhanced through this unified monitoring mechanism.^ The multi-objective ASIP design flow we have proposed and implemented is first of its kind. By adjusting the parameters used by the techniques applied in each step of the flow, the user can flexibly choose his/her design goal among a set of metrics, and explore the trade-offs among performance, energy efficiency, area efficiency, and security and reliability. ^